RegViz: Visualize GTCSR Bitfield

Renesas Electronics /R7FA4T1BB /GPT16E0 /GTCSR

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Interpret as GTCSR

CSELCC=0, CSELCE=0, CSGTRGCR=0, CSCBRAH=0, CSCAFBH=0, CSGTRGDR=0, CSCBRAL=0, CSGTRGBR=0, CSELCD=0, CSGTRGCF=0, CSELCB=0, CSCARBL=0, CSCAFBL=0, CSELCG=0, CCLR=0, CSCARBH=0, CSGTRGAR=0, CSELCF=0, CSELCA=0, CSCBFAL=0, CSGTRGDF=0, CSELCH=0, CSCBFAH=0, CSGTRGBF=0, CSGTRGAF=0

Description

General PWM Timer Clear Source Select Register

Fields

CSGTRGAR	GTETRGA Pin Rising Input Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTETRGA input 1 (1): Counter clear enabled on the rising edge of GTETRGA input
CSGTRGAF	GTETRGA Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGA input 1 (1): Counter clear enabled on the falling edge of GTETRGA input
CSGTRGBR	GTETRGB Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGB input 1 (1): Enable counter clear on the rising edge of GTETRGB input
CSGTRGBF	GTETRGB Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGB input 1 (1): Counter clear enabled on the falling edge of GTETRGB input
CSGTRGCR	GTETRGC Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGC input 1 (1): Enable counter clear on the rising edge of GTETRGC input
CSGTRGCF	GTETRGC Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGC input 1 (1): Counter clear enabled on the falling edge of GTETRGC input
CSGTRGDR	GTETRGD Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGD input 1 (1): Enable counter clear on the rising edge of GTETRGD input
CSGTRGDF	GTETRGD Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGD input 1 (1): Counter clear enabled on the falling edge of GTETRGD input
CSCARBL	GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
CSCARBH	GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
CSCAFBL	GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
CSCAFBH	GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
CSCBRAL	GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
CSCBRAH	GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
CSCBFAL	GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
CSCBFAH	GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
CSELCA	ELC_GPTA Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTA input 1 (1): Counter clear enabled at the ELC_GPTA input
CSELCB	ELC_GPTB Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTB input 1 (1): Counter clear enabled at the ELC_GPTB input
CSELCC	ELC_GPTC Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTC input 1 (1): Counter clear enabled at the ELC_GPTC input
CSELCD	ELC_GPTD Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTD input 1 (1): Counter clear enabled at the ELC_GPTD input
CSELCE	ELC_GPTE Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTE input 1 (1): Counter clear enabled at the ELC_GPTE input
CSELCF	ELC_GPTF Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTF input 1 (1): Counter clear enabled at the ELC_GPTF input
CSELCG	ELC_GPTG Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTG input 1 (1): Counter clear enabled at the ELC_GPTG input
CSELCH	ELC_GPTH Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTH input 1 (1): Counter clear enabled at the ELC_GPTH input
CCLR	Software Source Counter Clear Enable 0 (0): Counter clear disabled by the GTCLR register 1 (1): Counter clear enabled by the GTCLR register

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